1. Field of the Invention
The present invention relates to fabrication of a semiconductor device, and more particularly to a method for fabricating a bipolar transistor in which emitter, base and collector are vertically self-aligned.
2. Description of the Prior Art
To enhance operation characteristics of a semiconductor switching device in the semiconductor field, several types of hereto-junction bipolar transistors have been developed. Typical one of them has a SiGe base which is substituted for a silicon base and has a characteristic of narrowing in energy band gap and grading dependently upon Ge content of the SiGe base.
Since such a hereto-junction bipolar transistor, similar to a well-known homo-junction transistor, is fabricated by using a polysilicon as a material for forming base and emitter regions as well as an impurity diffusing Source of the emitter region and using a SiGe base so as to increase an emitter injection efficiency, and the base region is formed by an ultra-thin film doped with an impurity of high concentration, the hereto-junction bipolar transistor is significantly improved in a current gain and a switching speed.
Recently, as the integration of a semiconductor device is increasingly enhanced, i.e. as a semiconductor device is further scaled down in size, a selectively epitaxial growth has been developed to reduce a parasitic capacitance occurring in a base on an active region of the device and occurring between base and collector thereof. Also, to form a thin base electrode, a metallic silicide (TiSi.sub.2) in place of a polysilicon is used.
FIG. 1 shows the construction of a prior art hereto-junction bipolar transistor in which a base is formed by a super self-aligned selectively epitaxial grown.
The fabricating method of the prior art hetero-junction bipolar transistor will be described below with reference to FIG. 1.
First, after sequentially forming an n.sup.+ type subcollector 1, an n.sup.+ type collector 3 and a collector sinker 16 on a substrate 1, a trench isolation is carried out to form a trench in the substrate 1. Then, an insulating material is filled into the trench to form an insulating layer 4 for device-isolating.
Also, an active region of the transistor is defined by forming a pattern composed of an insulating layer 5, a p+ type polysilicon layer 6, an insulating layer 7 and a side wall nitride layer 8, and then an impurity is ion-injected into the active region to form an n-type collector region 9, whereby a high-current characteristic of the transistor can be improved.
Next, in the active region formed thus, a SiGe base 10 serving as an intrinsic base and a polysilicon layer 11 for electrically connecting between the p+ type polysilicon layer 6 and the base 10 are sequentially grown by using a gas source MBE (molecular beam epitaxy). Therefore, a parasitic capacitance region formed between the collector and the base is limited within a width of the polysilicon layer 11 only.
Finally, after formation of a side wall insulating layer 12 on the intrinsic base 10 by a well-known anisotropic etching method, an emitter 13 is self-aligned and electrodes 15 is formed thereon, as shown in FIG. 1.
As described above, the intrinsic base 10 is composed of SiGe so as to increase an emitter injection efficiency, and the collector-base and emitter-base all are self-aligned. Also, since a parasitic capacitance region of the base is limited within a region corresponding to the side wall nitride layer 8 and the side wall insulating layer 12, the parasitic capacitance can be reduced dependently on controlling the total width of the side wall nitride and insulating layers 8, 12.
However, in fabrication sequence, it is not preferable to form the polysilicon layer 11 of a predetermined pattern by using a horizontal wet-etching of the insulating layer 5 and to define the parasitic capacitance region between the collector and the base, because such a fabrication sequence is seriously lowered in a uniform stability and a reproduction thereof. As a result, an performance of the device fabricated thus is seriously lowered.
Furthermore, in order to form the base 10 and the polysilicon layer 11, an extremely slow, selective thin film growth must be performed two times. Since component materials of them also are different from each other, the forming processes of them are very complicated. Thus, there arises the problem that a yield of production is lowered.
In addition, if a polysilicon is extremely slightly grown on the thin film base 10, there arises the problem that such an extremely thin film base exerts a seriously bad influence on the device due to occurrence of a defect therein.